1. Field of the Disclosure
The disclosure relates to a flash memory device and a method for driving the same, and more particularly to a flash memory device which can reduce a program time or erase time by varying an initial pulse width or an initial bias level in a program operation or erase operation using an Incremental Step Pulse Programming (ISPP) scheme, and a method for driving the same.
2. Discussion of Related Art
Among nonvolatile memory devices such as an Electrically Erasable and Programmable Read Only Memory (EEPROM) and a flash memory, a NOR type nonvolatile memory device which performs a data program operation by injecting electrons into a floating gate by channel hot electron injection has been widely used. The NOR type nonvolatile memory device programs data of eight memory cells at a time in byte units, namely, in parallel due to current restrictions, and thus is disadvantageous in program speed.
Recently, a NAND type flash memory device which performs a data program operation by injecting electrons into a floating gate by Fowler-Nordheim (FN) tunneling, and which provides high capacity and high integration has been suggested due to the above problems of the NOR type nonvolatile memory device. Since the NAND type flash memory device requires a small operation current in the data program operation, the NAND type flash memory device is easily provided with the current from a boosting circuit in the chip and easily operated with a single current. Accordingly, the NAND type flash memory device can perform the data program operation on memory cells connected to a selected word line in page units, namely collectively program the memory cells, thereby increasing a program speed.
In the data program operation of the NAND type flash memory device, if heterogeneity of program characteristics resulting from heterogeneity of a process is serious, a program speed difference between the memory cells connected to the selected word line increases, a repetition number of program and verify operations increases, and thus a program speed decreases. Here, heterogeneity of the program speed resulting from heterogeneity of the process generates about two orders of program time difference between the memory cells of the selected word line. Therefore, in a repetitive application method of simple program pulses having the same pulse voltage value and the same pulse time width, the program and verify operations must be performed about 100 times. In this case, the time taken to convert a voltage of the program and verify operations is much longer than a time taken to apply a program voltage, which results in a low program speed.
In order to solve the foregoing problems, the number of the program and verify operations must be restricted to about ten times. For this, the general repetitive application method of the simple program pulses needs to apply program pulses having a slightly higher pulse voltage value. However, the memory cell having the highest program speed is over-programmed, thereby increasing heterogeneity of a program threshold voltage.
So as to solve the aforementioned problems, a new program method of a NAND type flash memory device which can restrict the number of program and verify operations without increasing heterogeneity of a program threshold voltage has been disclosed in '95 ISSCC (“A 3.3V 32Mb NAND Flash Memory with ISPP Scheme), p. 128 fF. According to the ISPP scheme, when a program operation is repetitively performed, a high program voltage applied to a selected word line is set as a variable voltage value gradually increasing according to increase of a number of program operations, and a voltage applied to a bit line is set as a predetermined voltage value regardless of the number of the program operations. Therefore, when the data program operation is performed, the program voltage difference gradually increases according to the increase of the number of the program operations.
In the data program operation using the ISPP scheme, the memory cell is programmed according to increase of the number of the program operations. Even if the program threshold voltage increases, the gradually-increasing program word line voltage compensates for reduction of a potential of the floating gate. As a result, an electric field applied to a tunnel oxide film of the memory cell is always maintained constant.
However, as shown in FIGS. 1A and 1B, an initial pulse width or an initial bias level is fixedly applied to the whole pages in the program or erase operation. In case program or erase characteristics are deteriorated due to variations of the process or cycling, the threshold voltage of the cell is rarely varied in application of the initial program or erase pulse. Accordingly, the whole program or erase time increases.